1. Field of the Invention
The present invention relates to a MOS voltage-to-current converter circuit employing a field-effect MOS transistor formed on a semiconductor integrated circuit chip. More specifically, the invention relates to a MOS differential voltage-to-current converter circuit which suppresses fluctuation of a mutual conductance.
2. Description of the Related Art
Construction and operation of the conventional MOS differential voltage-to-current converter circuit will be discussed with reference to the drawings. Throughout the disclosure, a field-effect MOS transistor will be simply referred to as "MOSFET", N-channel field-effect MOS transistor will be referred to as "NMOSFET", and similarly, P-channel field-effect MOS transistor will be referred to as "PMOSFET".
Concerning the reference signs to be used in the following disclosure, I, I*, I**, .DELTA.I represent current, V, V*, V**, .DELTA.V represent voltage, R, R*, R** represent resistance, .beta., .beta.* represent gain coefficient of MOSFET, and gm, gm* represent mutual conductance of the differential voltage-to-current converter circuit.*,** represent numerals.
One example of the circuit construction of the conventional differential voltage-to-current converter circuit (hereinafter referred to as "first prior art") is illustrated in FIG. 13. In FIG. 13, N.sub.1 and N.sub.2 represent first and second NMOSFET, 2R.sub.0 represents one source resistance (resistance value 2R.sub.0) mutually connecting the source terminals of N.sub.1 and N.sub.2. V.sub.1 and V.sub.2 represent first and second input voltages of the differential voltage-to-current converter circuit, V.sub.B1 and V.sub.B2 represent backgate voltages. On the other hand, I.sub.01 and I.sub.02 represent first and second constant current sources, respectively. I.sub.1 and I.sub.2 represent first and second output currents of the differential voltage-current converter circuit, respectively.
Note that various equations, numbered (1)-(50), are referenced hereinafter. The definition of each equation is also provided hereinafter, with related equations grouped together following their corresponding discussion.
Here, it is assumed that currents I.sub.01 and I.sub.02 of the first and second constant current sources are equal to each other. Double of the current I.sub.01 or I.sub.02 is defined as a constant current I.sub.00 which is expressed by the equation (1). A differential output current .DELTA.I (I.sub.1 -I.sub.2) and a differential input voltage .DELTA.V (V.sub.1 -V.sub.2) are respectively expressed by the equation (2).
Discussion is now given for an input/output characteristics of the differential input voltage .DELTA.V and the differential output current .DELTA.I in the differential voltage-to-current converter circuit of FIG. 13. Assuming the gain coefficient of the MOSFET is .beta., a drain current I.sub.0 is expressed by the following equation (3) in the saturated range. It should be noted that, in the equation (3), V.sub.GS represents a gate-source voltage, V.sub.T represents a threshold voltage. Accordingly, V.sub.GS can be expressed by the equation (4).
Applying Kirchhoff's law in the loops of V.sub.1 .about.V.sub.GS1 .about.V.sub.2R0 V.sub.GS2 .about.V.sub.2, the equation (5) can be established. Then, the differential input voltage .DELTA.V can be expressed by the equation (6) with where the current flowing through a resistor 2R.sub.0 between the sources is I.sub.R0. It should be appreciated that, the gain coefficients .beta. of N.sub.1 and N.sub.2 forming differential pair in equation (6) are mutually equal.
From Kirchhoff's law, the equation (7-a) can be established with respect to both ends of the resistor 2R.sub.0. Therefore, the current I.sub.R0 flowing through the source resistor 2R.sub.0 is expressed by the equation (7-b). Therefore, first and second output currents I.sub.1 and I.sub.2 are expressed by the equation (7-c). Substituting the equation (6) with these, the equation (8), which expresses the input/output characteristics of the differential input voltage .DELTA.V and the differential output current .DELTA.I, can be derived.
The input/output characteristics of the differential voltage-to-current converter circuit of the first prior art, which is expressed by the equation (8), is illustrated as curve a in FIG. 14. A reciprocal of the mutual conductance g.sub.m of the differential voltage-to-current converter circuit can be obtained by differentiating .DELTA.V with the differential output current .DELTA.I, and expressed by the equation (9). As shown in FIG. 14, the mutual conductance g.sub.m becomes the maximum value g.sub.mmax when the differential input voltage .DELTA.V is 0. At this time, from the equation (8), .DELTA.I becomes 0, the reciprocal of the maximum value g.sub.mmax is expressed by the equation (10). It should be appreciated that the maximum value g.sub.mmax of the mutual conductance corresponds to the gradient of a tangent b of the input/output characteristics curve a of FIG. 14 at .DELTA.V=0, the tangent b is expressed by: EQU .DELTA.I=g.sub.mmax .times..DELTA.V
A coefficient E expressing non-linearity of the input/output characteristics of the differential voltage-to-current converter circuit is defined by the equation (12-a). Namely, the non-linearity E can be obtained by obtaining a difference between the input/output characteristics curve a and the tangent b with respect to .DELTA.V and by dividing the difference by the value (g.sub.mmax .times..DELTA.V) of the tangent b.
Expressing the a rate of I.sub.00 as double of the current of the first and second current source and the differential output current .DELTA.I as a coefficient .alpha. (equation (11)), the non-linearity E can be expressed with the coefficient .alpha. and I.sub.00 in the equation (12-b). A curve in FIG. 15 is a plot of the non-linearity with respect to the differential input voltage .DELTA.V (horizontal axis).
Respective values shown in FIGS. 14 and 15 are derived with taking the constant current I.sub.00 =1 (mA), gain coefficient .beta.=1.times.10.sup.-3 (A/V.sub.2), the source resistor R.sub.0 =1 (k.OMEGA.). It should be noted that the value (horizontal axis) of the non-linearity E is shown by % in FIG. 15. With reference to FIG. 15, at near the maximum value I.sub.00 of the differential output current the non-linearity E becomes approximately 17%. ##EQU1##
From FIGS. 14 and 15, it should be appreciated that the absolute value of the non-linearity E is increased according to increasing of the differential output current .DELTA.I associated with increasing of the differential input voltage .DELTA.V. This is caused due to I.sub.D -V.sub.GS characteristics of the MOSFET, in which a drain current I.sub.n does not vary in proportion to variation of a gate-source voltage V.sub.GS. In other words, as expressed in the equation (8), this is caused due to the fact that the differential input voltage .DELTA.V and the voltage V.sub.2R0 at opposite ends of the source resistor (accordingly, the differential output current .DELTA.I) are not proportional to each other.
The characteristics of the above-mentioned differential voltage-to-current converter circuit is similarly applicable for the case where the first and second NMOSFETs are replaced with PMOSFETs.
FIGS. 16 shows another example of a circuit construction of a conventional differential voltage-to-current converter circuit in which first and second resistors R.sub.01 and R.sub.02 are connected in common (hereinafter referred to as "second prior art"). As shown in FIG. 16, the second prior art is constructed by connecting one end of first and second resistors R.sub.01 and R.sub.02 to source terminals of first and second MOSFETs N.sub.1 and N.sub.2, respectively, and connecting one constant current source I.sub.0 to a common junction of the other end of first and second resistors R.sub.01 and R.sub.02. V.sub.1 and V.sub.2 denote first and second inputs voltages, V.sub.B1 and V.sub.B2 denote a backgate terminal voltages, and I.sub.1 and I.sub.2 denote the first and second output currents.
The resistance values of the first and second resistors R.sub.01 and R.sub.02 are assumed to be equal to each other. Then, the source resistance R.sub.00 is defined as expressed in the equation (13-a). Also, the differential output current .alpha.I is defined to be expressed by the following equation (13-b).
The differential input voltage .DELTA.V in the differential voltage-to-current converter circuit of FIG. 16 is derived in the similar manner to the foregoing first prior art by replacing the source resistor 2R.sub.0 with 2R.sub.00 and I.sub.00 in the equation (1) with I.sub.0, and thus is expressed by the equation (14). The input/output characteristics of the second prior art is illustrated in FIG. 17, and the non-linearity E defined by the equation (18) is illustrated in FIG. 18. ##EQU2##
Respective values in FIGS. 17 and 18 are derived with assumption of constant current source I.sub.0 =1 (mA), gain coefficient .beta.=1.times.10.sup.-3 (A/V.sub.2), source resistance R.sub.00 =1 (K.OMEGA.).
From FIGS. 17 and 18, it should be appreciated that the absolute value of the non-linearity E is increased according to increasing of the differential output current .DELTA.I associated with increasing of the differential input voltage .DELTA.V. This is caused due to I.sub.D -V.sub.GS characteristics of the MOSFET, in which a drain current I.sub.n does not vary in proportion to variation of a gate-source voltage V.sub.GS. In other words, as expressed in the equation (14), this is caused due to the fact that the differential input voltage .DELTA.V and the voltage V.sub.R at opposite ends of the source resistor (accordingly, the differential output current .DELTA.I) are not proportional to each other.
The characteristics of the above-mentioned the differential voltage-to-current converter circuit is similarly applicable for the case where the first and second NMOSFETs are replaced with PMOSFETs.
FIG. 19 shows a circuit construction of the differential voltage-to-current converter circuit disclosed in Japanese Unexamined Patent Publication No. 57-46161 (hereinafter referred to as "third prior art"). As shown in FIG. 19, the third prior art is designed for eliminating non-linearity of an amplifier element by combination of a differential amplifier and bipolar current-mirror circuit having two outputs.
In the third prior art, assuming the current-mirror circuit and the constant current source are both ideal, the relationship between the differential output current .DELTA.I and the differential input voltage .DELTA.V can be expressed by the equation (21). The input/output characteristics is shown in FIG. 20. The non-linearity E (expressed by the equation (22)) of the differential voltage-to-current converter circuit of the third prior art is illustrated in FIG. 21. From FIG. 21, the non-linearity E becomes 0 in a range of the differential input voltage .DELTA.V being .+-.RI.sub.0 /3. Therefore, a linearity can be improved.
However, in the third prior art, in order to take the current out, it becomes necessary to add a new circuit, such as an output side transistor added for the bipolar current-mirror circuit. This circuit varies signals in non-linear fashion according to variation of the input current. Therefore, the non-linearity of the voltage-to-current converter circuit is increased beyond 0 in the equation (22) to degrade the effect in improvement of the linearity.
As shown in FIGS. 20, 21, with the circuit construction in the third prior art, the range of the differential current, in which the non-linearity can be reduced, is in a range of 1/3 of the constant current I.sub.0. Accordingly, in order to obtain the output comparable with those in the prior arts 1 and 2, the constant current has to be three time grater, or, in the alternative, a size ratio between the bipolar transistors forming the mirror-current circuit has to be selected appropriately. ##EQU3## In FIG. 22, the construction of the differential amplifier disclosed in Japanese Unexamined Utility Model Publication No. 63-44521 (hereinafter referred to as "fourth prior art"). In FIG. 23, the input/output characteristics of the fourth prior art is illustrated.
In the fourth prior art, for respective first and second bipolar transistors, third and fourth bipolar transistors, bases and emitters of which are mutually connected, are employed. By applying the constant current to this, the linearity of the differential amplifier circuit is improved in the range of .+-..alpha.I.sub.EE /2 of the output current.
As shown in FIG. 22, in the circuit construction of the fourth prior art, direct current is constantly applied to input signal sources V.sub.1 and V.sub.2 from emitters of fifth and sixth transistors Q.sub.4 and Q.sub.5. Therefore, the input signal sources V.sub.1 and V.sub.2 require drive performance for supplying the supplied current.
FIGS. 24 and 25 show a circuit construction of a differential amplifier disclosed in Japanese Unexamined Patent Publication No. 59-229909 (hereinafter referred to as "fifth prior art"). As shown, the differential amplifier of the fifth prior art is constructed by contacting the drain of a first FET forming a differential pair to a load, the drain of a second FET forming the differential pair to the source of a third FET, and the gate of the third FET to a junction between the drain and the load of the first FET, and the drain of the third FET to the load.
In the fifth prior art, the relationship between the input voltage and the output voltage of the differential amplifier in the range where the mutual conductance g.sub.m1 to g.sub.m4 of the FETs (M1 to M4) satisfy the condition expressed in the equation (23), becomes as expressed in the equation (24). Then, the linearity of the input/output characteristics can be improved. ##EQU4##
The condition defined in the equation (23) with respect to the differential amplifier of the fifth prior art can be only satisfied by a fine signal alternating operation near a certain direct current operation point of the circuit (in the case where amplitude of the voltage at respective points in the circuit is small).
In the MOS differential voltage-to-current converter circuit in the foregoing first, second and fifth prior arts, a problem in degradation of the linearity of the input/output characteristics according to increasing of the differential output current .DELTA.I associated with increasing of the differential input voltage .DELTA.V and narrowing of a dynamic range, is encountered. There is further encountered a problem in increasing of non-linearity due to influence of variation of the properties of MOSFET, such as nonlinearity of I.sub.D -V.sub.GS characteristics, fluctuation of gain coefficient .beta., variation of a threshold voltage V.sub.T due to a backgate effect, variation of I.sub.D -I.sub.GS characteristics up to MOS saturation range due to short channel effect and so forth.
The third prior art is capable of reducing non-linearity of the differential amplifier circuit by combination of the differential amplifier circuit and the current-mirror circuit with two outputs employing the bipolar process. However, a new circuit is required for taking the current out. Also, the amplitude of the differential output current is merely 1/3 of the current value I.sub.0 of the constant current source at the greatest.
Accordingly, in the third prior art, it becomes necessary to provide the constant current I.sub.0 three times greater in order to obtain comparable output to the first and second prior arts, or to appropriately adjust the size ratio of the bipolar transistors forming the current-mirror circuit. Therefore, there is encountered a problem in difficulty in reducing consumed current in the circuit construction of the third prior art.
Moreover, in the circuit construction of the third prior art, the currents flowing through the transistor of the bipolar current-mirror circuit and the differential MOSFET influence each other. For instance, since an Early voltage V.sub.A of the bipolar transistor is typically smaller than the Early voltage V.sub.A of the MOS transistor, the variation magnitude of the collector currents of the transistors Q.sub.1 and Q.sub.2 and the drain current of N.sub.1 and N.sub.2 in FIG. 19 becomes greater than that in the case where MOS transistors are employed as all transistors. Therefore, it becomes difficult to design the size and so forth of the transistor independently.
Furthermore, the third prior art comprises the MOS transistors and the bipolar transistors. For fabricating these different types of transistors on the common semiconductor chip, production process is inherently increased to cause rising of the production cost.
Next, in the circuit construction of the foregoing fourth prior art, it is required the direct current constantly flowing into the input signal source and thus requires a driving performance to supply the current to the input signal source. Also, the performance of the whole circuit is significantly influenced by the external circuit (power source). Therefore, this circuit encounters a problem in difficulty of handling.
In the differential amplifier of the fifth prior art, the condition expressed by the equation (23) is only satisfied by a fine signal alternating operation near certain direct current operation point of the circuit (in the case where amplitude of the voltage at respective points in the circuit is small) and cannot be satisfied when amplitude of the voltage is large.